3 search results - page 1 / 1 » 3D-Stacked Memory Architectures for Multi-core Processors |
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Three-dimensional integration enables stacking memory directly on top of a microprocessor, thereby significantly reducing wire delay between the two. Previous studies have examin...
IEEEPACT
2007
IEEE
13 years 11 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
SBACPAD
2008
IEEE
13 years 11 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...