3D-Stacked Memory Architectures for Multi-core Processors

Three-dimensional integration enables stacking memory directly on top of a microprocessor, thereby significantly reducing wire delay between the two. Previous studies have examined the performance benefits of such an approach, but all of these works only consider commodity 2D DRAM organizations. In this work, we explore more aggressive 3D DRAM organizations that make better use of the additional die-to-die bandwidth provided by 3D stacking, as well as the additional transistor count. Our simulation results show that with a few simple changes to the 3D-DRAM

• Type: Conference
• Year: 2008
• Where: ISCA
• Authors: Gabriel H. Loh
• Keywords: Commodity 2d Dram, DRAM Organizations, Enables Stacking Memory, Hardware, ISCA 2008