4 search results - page 1 / 1 » 64-bit floating-point FPGA matrix multiplication |
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
ERSA
2010
13 years 2 months ago
2010
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
FCCM
2007
IEEE
13 years 6 months ago
2007
IEEE
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
FCCM
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...