Sciweavers

6 search results - page 2 / 2
» 802.11a transmitter: a case study in microarchitectural expl...
Sort
View
HPCA
2008
IEEE
14 years 5 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...