9 search results - page 2 / 2 » A BIST Scheme for On-Chip ADC and DAC Testing |
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
A deterministic dynamic element matching (DEM) approach to ADC testing is introduced and compared with a common random DEM method. With both approaches, a highly non-ideal DAC is ...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysi...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
We examine frequency-domain issues in the design and selection of on-chip test generators for built-in self-test (BIST) of highperformance digital filters. Test-generator/circuit...