Sciweavers

90 search results - page 1 / 18
» A Basis for Formal Robustness Checking
Sort
View
ISQED
2008
IEEE
117views Hardware» more  ISQED 2008»
13 years 11 months ago
A Basis for Formal Robustness Checking
Correct input/output behavior of circuits in presence of internal malfunctions becomes more and more important. But reliable and efficient methods to measure this robustness are ...
Görschwin Fey, Rolf Drechsler
ICRE
2000
IEEE
13 years 9 months ago
Requirements Documentation: Why a Formal Basis is Essential
Unless you have a complete and precise description of your product’s requirements, it is very unlikely that you will satisfy those requirements. A requirements document that is ...
David Lorge Parnas
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
13 years 11 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...
ACSD
2003
IEEE
87views Hardware» more  ACSD 2003»
13 years 10 months ago
Separation of Concerns in the Formal Design of Real-Time Shared Data-Space Systems
This paper proposes a formal framework for the design of real-time shared data-space systems. The proposed method separates the concerns of functionality, behavior, and timing. Th...
Mohammad Reza Mousavi, Michel A. Reniers, Twan Bas...
FM
2006
Springer
169views Formal Methods» more  FM 2006»
13 years 8 months ago
PSL Model Checking and Run-Time Verification Via Testers
Abstract. The paper introduces the construct of temporal testers as a compositional basis for the construction of automata corresponding to temporal formulas in the PSL logic. Temp...
Amir Pnueli, Aleksandr Zaks