ISQED 2008 - PDF Preprint Papers

ISQED 2008 International Symposium on Quality Electronic Design

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ISQED-2008 Paper

click to vote

ISQED
2008
IEEE

186views Hardware» more ISQED 2008»

Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems

13 years 11 months ago

Download cs.ucla.edu

—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...

Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	186	Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems	claim
2	154	Error Protected Data Bus Inversion Using Standard DRAM Components	claim
3	153	ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis	claim
4	153	Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding	claim
5	151	Quality of a Bit (QoB): A New Concept in Dependable SRAM	claim
6	150	Fundamental Data Retention Limits in SRAM Standby Experimental Results	claim
7	150	Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates	claim
8	142	Clock Skew Analysis via Vector Fitting in Frequency Domain	claim
9	124	Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design	claim
10	120	Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation	claim
11	119	Instruction Scheduling for Variation-Originated Variable Latencies	claim
12	118	A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors	claim
13	117	A Basis for Formal Robustness Checking	claim
14	115	Elastic Timing Scheme for Energy-Efficient and Robust Performance	claim
15	112	Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas	claim
16	109	Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation	claim
17	103	Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics	claim
18	103	Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation	claim
19	101	Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations	claim
20	98	Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)	claim
21	94	Processor Verification with hwBugHunt	claim
22	92	Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution	claim
23	86	Improving the Efficiency of Power Management Techniques by Using Bayesian Classification	claim
24	85	A Statistic-Based Approach to Testability Analysis	claim
25	79	Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method	claim
26	66	An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers