54 search results - page 1 / 11 » A Bus Delay Reduction Technique Considering Crosstalk |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem f...
IOLTS
2003
IEEE
13 years 9 months ago
2003
IEEE
In this paper we present a technique which allows to reduce the crosstalk-induced delay within busses implementing an error detecting/correcting code. This technique is based on t...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
With the exponential reduction in the scaling of feature size, inter-wire coupling capacitance becomes the dominant part of load capacitance. Two problems are introduced by coupli...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...