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2000
IEEE

A Bus Delay Reduction Technique Considering Crosstalk

11 years 9 months ago
A Bus Delay Reduction Technique Considering Crosstalk
As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on delay increase caused by crosstalk. On-chip bus delay is maximized by crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for repeaterinserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5% to 20% can be achieved.
Kei Hirose, Hiroto Yasuura
Added 30 Jul 2010
Updated 30 Jul 2010
Type Conference
Year 2000
Where DATE
Authors Kei Hirose, Hiroto Yasuura
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