54 search results - page 9 / 11 » A Bus Delay Reduction Technique Considering Crosstalk |
DAC
2004
ACM
14 years 6 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
ICC
2007
IEEE
14 years 3 days ago
2007
IEEE
— Selected mapping (SLM) is a well-known method for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency-division multiplexing (OFDM) systems. The main drawbac...
DATE
2008
IEEE
14 years 7 days ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
SAC
2010
ACM
13 years 6 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
ISQED
2005
IEEE
13 years 11 months ago
2005
IEEE
Leakage power has become one of the most critical design concerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power wit...