3 search results - page 1 / 1 » A CMOS Clock and Data Recovery Circuit with a Half-Rate Thre... |
IEICET
2006
13 years 5 months ago
2006
DAC
2001
ACM
14 years 6 months ago
2001
ACM
This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
—A novel clock and data recovery architecture with adaptive loop gain is proposed for spread spectrum SerDes applications such as the Serial AT Attachment. The proposed design co...