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ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
13 years 10 months ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
SODA
2001
ACM
125views Algorithms» more  SODA 2001»
13 years 6 months ago
Parallel processor scheduling with delay constraints
We consider the problem of scheduling unit-length jobs on identical parallel machines such that the makespan of the resulting schedule is minimized. Precedence constraints impose ...
Daniel W. Engels, Jon Feldman, David R. Karger, Ma...
ISHPC
2003
Springer
13 years 10 months ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos
CF
2010
ACM
13 years 9 months ago
Variant-based competitive parallel execution of sequential programs
Competitive parallel execution (CPE) is a simple yet attractive technique to improve the performance of sequential programs on multi-core and multi-processor systems. A sequential...
Oliver Trachsel, Thomas R. Gross