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» A Design Method for Heterogeneous Adders
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DATE
2009
IEEE
139views Hardware» more  DATE 2009»
13 years 11 months ago
Enhanced design of filterless class-D audio amplifier
In this work, we propose an enhanced design method for filterless class-D audio amplifier based on multilevel architecture. The multilevel technique consists of a multilevel conve...
Chun Wei Lin, Bing-Shiun Hsieh, Yu Cheng Lin
ARITH
2007
IEEE
13 years 11 months ago
Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
Liang-Kai Wang, Michael J. Schulte
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
13 years 9 months ago
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders
—As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the co...
Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park
DAC
2004
ACM
14 years 5 months ago
A method to decompose multiple-output logic functions
This paper shows a method to decompose a given multipleoutput circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represe...
Tsutomu Sasao, Munehiro Matsuura
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
13 years 10 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...