126 search results - page 3 / 26 » A Design Methodology for the Exploitation of High Level Comm... |
ISQED
2007
IEEE
13 years 12 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...
ICCD
1992
IEEE
13 years 9 months ago
1992
IEEE
Current synthesis methodologies based on hardwaredescription languages focus mainly on two distinct levels: behavior and register-transfer levels. In many practical cases, however...
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
TCAD
2011
13 years 1 days ago
2011
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...