103 search results - page 1 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
MTDT
2002
IEEE
13 years 9 months ago
2002
IEEE
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip sel...
EDCC
1999
Springer
13 years 9 months ago
1999
Springer
Abstract. The paper presents a new approach to transparent BIST for wordoriented RAMs which is based on the transformation of March transparent test algorithms to the symmetric ver...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
: It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior. This means that, given a fault model, it should be possible...