Sciweavers

103 search results - page 20 / 21
» A Fault Modeling Technique to Test Memory BIST Algorithms
Sort
View
LCTRTS
2009
Springer
14 years 16 days ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
14 years 16 days ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon
AMOST
2007
ACM
13 years 9 months ago
Using LTL rewriting to improve the performance of model-checker based test-case generation
Model-checkers have recently been suggested for automated software test-case generation. Several works have presented methods that create efficient test-suites using model-checker...
Gordon Fraser, Franz Wotawa
CORR
2010
Springer
206views Education» more  CORR 2010»
13 years 5 months ago
Detecting Anomalous Process Behaviour using Second Generation Artificial Immune Systems
Abstract. Artificial immune systems (AISs) are problem-solving systems inspired by the biological immune system. They have been successfully applied to a number of problem domains ...
Jamie Twycross, Uwe Aickelin, Amanda M. Whitbrook
SIGMOD
2007
ACM
186views Database» more  SIGMOD 2007»
14 years 5 months ago
Fg-index: towards verification-free query processing on graph databases
Graphs are prevalently used to model the relationships between objects in various domains. With the increasing usage of graph databases, it has become more and more demanding to e...
James Cheng, Yiping Ke, Wilfred Ng, An Lu