3 search results - page 1 / 1 » A Floorplan-Based Planning Methodology for Power and Clock D... |
DAC
1999
ACM
13 years 9 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
ISPD
2004
ACM
13 years 10 months ago
2004
ACM
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...