Challenges in clockgating for a low power ASIC methodology

Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the logic modules as well as by eliminating power dissipation in the clock distribution network.There is an inherent pitfall though in implementinggating groupsfor hierarchical gated clock distribution because the groups are typically developed at the logic level with no informationofthe physical layout ofthe clocktree. Depending on the distribution of underlying sinks, maintaining gating groups can cause a wiring overhead that is potentially greater than the savings due to reduced switching. We look at modifcations of zeroskew tree algorithms to consider both the physical and logical aspects of hierarchical gating. The algorithms are applied to data takenfrom a low power ASIC design. The best gated clocktree is created using both physical and logical information.

• Type: Conference
• Year: 1999
• Where: ISLPED
• Authors: David Garrett, Mircea R. Stan, Alvar Dean
• Keywords: Gating, Hardware, Hierarchical Gated Clock, ISLPED 1999, Low Power