154 search results - page 2 / 31 » A Formal Verification Approach for IP-based Designs |
BIRTHDAY
2007
Springer
13 years 9 months ago
2007
Springer
We present a verification methodology for cooperating traffic agents covering analysis of cooperation strategies, realization of strategies through control, and implementation of c...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...