Evaluating coverage of error detection logic for soft errors using formal methods

—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and correction logic. We describe an easily portable approach, which can be applied to a wide variety of multi-GHz industrial designs.

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Udo Krautz, Matthias Pflanz, Christian Jacobi 0002, Hans-Werner Tast, Kai Weber, Heinrich Theodor Vierhaus
• Keywords: DATE 2006, Fault-tolerant Designs, Formal Verification Approach, Hardware, Multi-GHz Industrial Designs