24 search results - page 2 / 5 » A Framework for Coarse-Grain Optimizations in the On-Chip Me... |
LCPC
2005
Springer
13 years 11 months ago
2005
Springer
The goal of this work is a systematic approach to compiler optimization for simultaneously optimizing across multiple levels of the memory hierarchy. Our approach combines compiler...
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
The development of efficient parallel out-of-core applications is often tedious, because of the need to explicitly manage the movement of data between files and data structures ...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we present a mechanism for automatic management of the memory hierarchy, including secondary storage, in the context of a global address space parallel programming ...