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ARC
2008
Springer
128views Hardware» more  ARC 2008»
13 years 6 months ago
A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures
Abstract. In this paper we present a framework for the automatic identification and selection of convex MIMO instruction-set extensions for reconfigurable architecture. The framewo...
Carlo Galuzzi, Koen Bertels
ERSA
2009
185views Hardware» more  ERSA 2009»
13 years 2 months ago
Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
Mariusz Grad, Christian Plessl
IPPS
2006
IEEE
13 years 10 months ago
An automated development framework for a RISC processor with reconfigurable instruction set extensions
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
Nikolaos Vassiliadis, George Theodoridis, Spiridon...
VLSID
2006
IEEE
119views VLSI» more  VLSID 2006»
14 years 5 months ago
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
ARC
2006
Springer
157views Hardware» more  ARC 2006»
13 years 8 months ago
PISC: Polymorphic Instruction Set Computers
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Won...