24 search results - page 1 / 5 » A Fully Asynchronous Superscalar Architecture |
IEEEPACT
1999
IEEE
13 years 9 months ago
1999
IEEE
An asynchronous superscalar architecture is presented based on a novel architectural feature called instruction compounding. This enables efficient dynamic scheduling and forwardi...
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
CHES
2006
Springer
13 years 9 months ago
2006
Springer
Abstract. We propose a superscalar coprocessor for high-speed curvebased cryptography. It accelerates scalar multiplication by exploiting instruction-level parallelism (ILP) dynami...
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. In this paper, a distributed re...
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...