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CPHYSICS
2010
135views more  CPHYSICS 2010»
13 years 5 months ago
An events based algorithm for distributing concurrent tasks on multi-core architectures
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...
David W. Holmes, John R. Williams, Peter Tilke
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
13 years 10 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
ISPAN
1997
IEEE
13 years 9 months ago
CASS: an efficient task management system for distributed memory architectures
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...
Jing-Chiou Liou, Michael A. Palis
IEEEPACT
2006
IEEE
13 years 11 months ago
Compiling for stream processing
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
Abhishek Das, William J. Dally, Peter R. Mattson
ISORC
2005
IEEE
13 years 11 months ago
On Real-Time Performance of Ahead-of-Time Compiled Java
One of the main challenges in getting acceptance for safe object-oriented languages in hard real-time systems is to combine automatic memory management with hard real-time constra...
Anders Nilsson, Sven Gestegard Robertz