48 search results - page 1 / 10 » A General Algorithm for Tiling the Register Level |
ICS
1998
Tsinghua U.
13 years 9 months ago
1998
Tsinghua U.
ICS
2009
Tsinghua U.
14 years 2 days ago
2009
Tsinghua U.
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
ICS
2004
Tsinghua U.
13 years 10 months ago
2004
Tsinghua U.
Storage mapping optimization is a flexible approach to folding array dimensions in numerical codes. It is designed to reduce the memory footprint after a wide spectrum of loop tr...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
BMCBI
2006
13 years 5 months ago
2006
Background: High density oligonucleotide tiling arrays are an effective and powerful platform for conducting unbiased genome-wide studies. The ab initio probe selection method emp...