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» A Generic Dual Core Architecture with Error Containment
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CN
2008
109views more  CN 2008»
13 years 5 months ago
CoCONet: A collision-free container-based core optical network
Electrical-to-optical domain conversions and vice versa (denoted by O/E/O conversions) for each hop in optical core transport networks impose considerable capital and financial ov...
Amin R. Mazloom, Preetam Ghosh, Kalyan Basu, Sajal...
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
13 years 8 months ago
On the Risk of Fault Coupling over the Chip Substrate
—Duplication and comparison has proven to be an efficient method for error detection. Based on this generic principle dual core processor architectures with output comparison ar...
Peter Tummeltshammer, Andreas Steininger
DSN
2007
IEEE
13 years 11 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
SIGCOMM
2010
ACM
13 years 5 months ago
Generic and automatic address configuration for data center networks
Data center networks encode locality and topology information into their server and switch addresses for performance and routing purposes. For this reason, the traditional address...
Kai Chen, Chuanxiong Guo, Haitao Wu, Jing Yuan, Zh...
ERSA
2008
145views Hardware» more  ERSA 2008»
13 years 6 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione