Sciweavers

8 search results - page 2 / 2
» A Generic Standard Cell Design Methodology for Differential ...
Sort
View
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
14 years 17 days ago
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Ch...
TCAD
2008
98views more  TCAD 2008»
13 years 6 months ago
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
Khaled R. Heloue, Farid N. Najm
DAC
2002
ACM
14 years 7 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou