TCAD 2008 - PDF Preprint Papers

TCAD 2008

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TCAD
2008

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Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric

13 years 4 months ago

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Abstract--This paper proposes an algorithm that provides both dynamic voltage scaling and power shutdown to minimize the total energy consumption of an application executed on an o...

Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho A...

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Id	Views	Title	Status

1	215	Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric	claim
2	201	Bitmask-Based Code Compression for Embedded Systems	claim
3	195	Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs	claim
4	183	Systematic and Automated Multiprocessor System Design, Programming, and Implementation	claim
5	181	A Survey of Automated Techniques for Formal Software Verification	claim
6	172	General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing	claim
7	167	System-Level Dynamic Thermal Management for High-Performance Microprocessors	claim
8	136	A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation	claim
9	133	Metal-Density-Driven Placement for CMP Variation and Routability	claim
10	128	Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs	claim
11	127	Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration	claim
12	124	An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs	claim
13	120	Charge Recycling in Power-Gated CMOS Circuits	claim
14	119	FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design	claim
15	119	Bridging Fault Test Method With Adaptive Power Management Awareness	claim
16	119	Full-Chip Routing Considering Double-Via Insertion	claim
17	119	Energy and Performance Optimization of Demand Paging With OneNAND Flash	claim
18	118	CHIPS: Custom Hardware Instruction Processor Synthesis	claim
19	118	Variability-Aware Bulk-MOS Device Design	claim
20	116	Scalable Synthesis and Clustering Techniques Using Decision Diagrams	claim
21	115	Statistical Thermal Profile Considering Process Variations: Analysis and Applications	claim
22	115	Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories	claim
23	114	Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns	claim
24	114	Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog	claim
25	114	Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management	claim
26	114	RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm	claim
27	112	Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs	claim
28	112	A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips	claim
29	110	A Reactive and Cycle-True IP Emulator for MPSoC Exploration	claim
30	107	Power Grid Analysis and Optimization Using Algebraic Multigrid	claim
31	106	Track Routing and Optimization for Yield	claim
32	103	Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip	claim
33	103	Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems	claim
34	102	Quantum Circuit Simplification and Level Compaction	claim
35	102	Fault-Tolerant Distributed Deployment of Embedded Control Software	claim
36	101	ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs	claim
37	101	Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors	claim
38	100	Robust Clock Tree Routing in the Presence of Process Variations	claim
39	99	MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs	claim
40	98	Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models	claim
41	97	Encoding Large Asynchronous Controllers With ILP Techniques	claim
42	96	An Implicit Approach to Minimizing Range-Equivalent Circuits	claim
43	93	Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion	claim
44	93	Transforming Cyclic Circuits Into Acyclic Equivalents	claim
45	92	CMP Fill Synthesis: A Survey of Recent Studies	claim
46	92	IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level	claim
47	90	Application and Verification of Local Nonsemantic-Preserving Transformations in System Design	claim
48	89	A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning	claim
49	89	Scan Architecture With Align-Encode	claim
50	88	Self-Adaptive Data Caches for Soft-Error Reliability	claim
51	84	Buffering Interconnect for Multicore Processor Designs	claim
52	82	A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification	claim
53	81	Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring	claim
54	80	Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method	claim
55	75	Static Analysis of Transaction-Level Communication Models	claim
56	75	An Efficient Graph-Based Algorithm for ESD Current Path Analysis	claim
57	73	Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias	claim
58	68	A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations	claim
59	68	Highly Efficient Gradient Computation for Density-Constrained Analytical Placement	claim
60	66	Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking	claim
61	65	Fashion: A Fast and Accurate Solution to Global Routing Problem	claim
62	59	Dual-Vdd Buffer Insertion for Power Reduction	claim
63	55	Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process	claim
64	49	State-Sensitive X-Filling Scheme for Scan Capture Power Reduction	claim
65	49	Register File Power Reduction Using Bypass Sensitive Compiler	claim

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