Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate in...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
This paper presents a new approach to the automated generation of an initialization sequence for synchronous sequential circuits. Finding an initialization sequence is a hard task...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
Abstract We propose a novel approach to preserve the synchronizing sequences of a circuit after retiming. The significance of this problem stems from the necessity of maintaining c...
Maher N. Mneimneh, Karem A. Sakallah, John Moondan...
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
In current research, the minimum cycle times of finite state machines are estimated by computing the delays of the combinational logic in the finite state machines. Even though th...
William K. C. Lam, Robert K. Brayton, Alberto L. S...