41 search results - page 1 / 9 » A Hardware Implementation of Layer 2 MPLS |
DELTA
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a hardware architecture for layer 2 Multi Protocol Label Switching (MPLS). MPLS is a protocol framework used primarily to prioritize internet traffic and impro...
CCECE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a hardware/software co-design for Multi Protocol Label Switching (MPLS) using RSVP-TE as a signaling protocol. MPLS is the protocol framework on which the atte...
GLOBECOM
2009
IEEE
13 years 2 months ago
2009
IEEE
Abstract--In this paper we investigate hardware implementations of ciphering algorithms, SNOW 3G and the Advanced Encryption Standard (AES), for the acceleration of the protocol st...
MSS
2000
IEEE
13 years 9 months ago
2000
IEEE
We present a unique new implementation of MPI-IO (as defined in the recent MPI2 message passing standard) that is easy to use, fast, efficient, and complete. Our implementation ...
FPL
2003
Springer
13 years 10 months ago
2003
Springer
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-r...