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» A Hardware Packet Re-Sequencer Unit for Network Processors
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ARCS
2008
Springer
13 years 6 months ago
A Hardware Packet Re-Sequencer Unit for Network Processors
Michael Meitinger, Rainer Ohlendorf, Thomas Wild, ...
IMC
2004
ACM
13 years 10 months ago
Introducing scalability in network measurement: toward 10 Gbps with commodity hardware
The capacity of today's network links, along with the heterogeneity of their traffic, is rapidly growing, more than the workstation’s processing power. This makes the task ...
Loris Degioanni, Gianluca Varenni
FPL
2006
Springer
105views Hardware» more  FPL 2006»
13 years 8 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
ANCS
2010
ACM
13 years 2 months ago
The case for hardware transactional memory in software packet processing
Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services. With increasing numbers of programmable processor and acceler...
Martin Labrecque, J. Gregory Steffan
IPPS
2005
IEEE
13 years 10 months ago
A Hardware Acceleration Unit for MPI Queue Processing
With the heavy reliance of modern scientific applications upon the MPI Standard, it has become critical for the implementation of MPI to be as capable and as fast as possible. Th...
Keith D. Underwood, K. Scott Hemmert, Arun Rodrigu...