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» A Heuristic for Clock Selection in High-Level Synthesis
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ASPDAC
2008
ACM
87views Hardware» more  ASPDAC 2008»
13 years 11 months ago
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis
This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional...
Tsuyoshi Sadakata, Yusuke Matsunaga