ASPDAC 2008 - PDF Preprint Papers

ASPDAC 2008 Asia and South Pacific Design Automation Conference

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ASPDAC
2008
ACM

200views Hardware» more ASPDAC 2008»

Non-Gaussian statistical timing analysis using second-order polynomial fitting

13 years 6 months ago

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In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...

Lerong Cheng, Jinjun Xiong, Lei He

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Id	Views	Title	Status

1	200	Non-Gaussian statistical timing analysis using second-order polynomial fitting	claim
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3	174	Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty	claim
4	173	Experiences of low power design implementation and verification	claim
5	169	Buffered clock tree synthesis for 3D ICs under thermal variations	claim
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7	168	A fast two-pass HDL simulation with on-demand dump	claim
8	164	The Shining embedded system design methodology based on self dynamic reconfigurable architectures	claim
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10	160	Reconfigurable RTD-based circuit elements of complete logic functionality	claim
11	154	Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures	claim
12	154	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching	claim
13	151	High performance current-mode differential logic	claim
14	150	Constraint-free analog placement with topological symmetry structure	claim
15	150	Bus-aware microarchitectural floorplanning	claim
16	145	Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches	claim
17	137	Automatic interface synthesis based on the classification of interface protocols of IPs	claim
18	135	Analog circuit simulation using range arithmetics	claim
19	135	Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs	claim
20	135	Temperature-aware MPSoC scheduling for reducing hot spots and gradients	claim
21	135	Block cache for embedded systems	claim
22	134	Automatic re-coding of reference code into structured and analyzable SoC models	claim
23	130	Architecture-level thermal behavioral characterization for multi-core microprocessors	claim
24	129	Clock tree synthesis with data-path sensitivity matching	claim
25	127	Power grid analysis benchmarks	claim
26	127	A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing	claim
27	126	A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem	claim
28	126	DPlace2.0: A stable and efficient analytical placement based on diffusion	claim
29	124	MaizeRouter: Engineering an effective global router	claim
30	122	LP based white space redistribution for thermal via planning and performance optimization in 3D ICs	claim
31	122	Total power optimization combining placement, sizing and multi-Vt through slack distribution management	claim
32	120	A low-leakage current power 180-nm CMOS SRAM	claim
33	120	In-vehicle vision processors for driver assistance systems	claim
34	119	Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor	claim
35	119	A stochastic local hot spot alerting technique	claim
36	118	Statistical gate delay model for Multiple Input Switching	claim
37	117	Dependability, power, and performance trade-off on a multicore processor	claim
38	116	Faster projection based methods for circuit level verification	claim
39	115	An optimal algorithm for sizing sequential circuits for industrial library based designs	claim
40	115	GECOM: Test data compression combined with all unknown response masking	claim
41	114	NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks	claim
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43	108	Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm	claim
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45	107	Full-chip thermal analysis for the early design stage via generalized integral transforms	claim
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47	106	Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA	claim
48	106	Hierarchical Krylov subspace reduced order modeling of large RLC circuits	claim
49	106	Efficient symbolic multi-objective design space exploration	claim
50	106	Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof	claim
51	104	Low power clock buffer planning methodology in F-D placement for large scale circuit design	claim
52	104	Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering	claim
53	104	Variability-driven module selection with joint design time optimization and post-silicon tuning	claim
54	103	Reliability-aware design for nanometer-scale devices	claim
55	103	Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification	claim
56	102	Duo-binary circular turbo decoder based on border metric encoding for WiMAX	claim
57	101	Interconnect modeling for improved system-level design optimization	claim
58	100	Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages	claim
59	99	A delay model for interconnect trees based on ABCD matrix	claim
60	99	1-cc computer using UWB-IR for wireless sensor network	claim
61	98	A unified methodology for power supply noise reduction in modern microarchitecture design	claim
62	97	Small-area CMOS RF distributed mixer using multi-port inductors	claim
63	97	A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures	claim
64	95	Statistical power profile correlation for realistic thermal estimation	claim
65	95	MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks	claim
66	94	Distribution arithmetic for stochastical analysis	claim
67	94	Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival	claim
68	93	Scheduling with integer time budgeting for low-power optimization	claim
69	93	Ordered escape routing based on Boolean satisfiability	claim
70	92	Design space exploration for a coarse grain accelerator	claim
71	92	Decomposition based approach for synthesis of multi-level threshold logic circuits	claim
72	91	Heuristic power/ground network and floorplan co-design method	claim
73	91	Automatic generation of hardware dependent software for MPSoCs from abstract system specifications	claim
74	90	Vertical via design techniques for multi-layered P/G networks	claim
75	89	Efficient synthesis of compressor trees on FPGAs	claim
76	89	Load scheduling: Reducing pressure on distributed register files for free	claim
77	88	REWIRED - Register Write Inhibition by Resource Dedication	claim
78	87	An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis	claim
79	86	An MILP-based wire spreading algorithm for PSM-aware layout modification	claim
80	85	A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults	claim
81	85	ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip	claim
82	83	On reducing both shift and capture power for scan-based testing	claim
83	83	Run-time power gating of on-chip routers using look-ahead routing	claim
84	82	Software-cooperative power-efficient heterogeneous multi-core for media processing	claim
85	82	A fast incremental clock skew scheduling algorithm for slack optimization	claim
86	81	Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs	claim
87	81	A 1.2GHz delayed clock generator for high-speed microprocessors	claim
88	80	An innovative Steiner tree based approach for polygon partitioning	claim
89	78	Robust test generation for power supply noise induced path delay faults	claim
90	78	Handling partial correlations in yield prediction	claim
91	77	Soft error rate reduction using redundancy addition and removal	claim
92	77	Parallel fault backtracing for calculation of fault coverage	claim
93	77	Symmetry-aware placement with transitive closure graphs for analog layout design	claim
94	76	Block remap with turnoff: A variation-tolerant cache design technique	claim
95	76	A low-cost cryptographic processor for security embedded system	claim
96	76	Test vector chains for increased targeted and untargeted fault coverage	claim
97	74	Large-scale fixed-outline floorplanning design using convex optimization techniques	claim
98	73	Webpage-based benchmarks for mobile device design	claim
99	72	The future of semiconductor industry - A foundry's perspective	claim
100	72	Design rule optimization of regular layout for leakage reduction in nanoscale design	claim
101	72	A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application	claim
102	71	A slew-rate controlled output driver with one-cycle tuning time	claim
103	71	Multithreaded coprocessor interface for multi-core multimedia SoC	claim
104	70	Best ways to use billions of devices on a wireless mobile SoC	claim
105	70	VEBoC: Variation and error-aware design for billions of devices on a chip	claim
106	69	Fast, quasi-optimal, and pipelined instruction-set extensions	claim
107	65	Statistical noise margin estimation for sub-threshold combinational circuits	claim
108	62	Panel: Best ways to use billions of devices on a chip	claim

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