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NIPS
1998
13 years 6 months ago
A High Performance k-NN Classifier Using a Binary Correlation Matrix Memory
This paper presents a novel and fast k-NN classifier that is based on a binary CMM (Correlation Matrix Memory) neural network. A robust encoding method is developed to meet CMM in...
Ping Zhou, Jim Austin, John Kennedy
IJCNN
2006
IEEE
13 years 10 months ago
SOM-Based Sparse Binary Encoding for AURA Classifier
—The AURA k-Nearest Neighbour classifier associates binary input and output vectors, forming a compact binary Correlation Matrix Memory (CMM). For a new input vector, matching ve...
Simon O'Keefe
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 5 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
NPL
2006
137views more  NPL 2006»
13 years 4 months ago
Minimal Structure of Self-Organizing HCMAC Neural Network Classifier
The authors previously proposed a self-organizing Hierarchical Cerebellar Model Articulation Controller (HCMAC) neural network containing a hierarchical GCMAC neural network and a ...
Chih-Ming Chen, Yung-Feng Lu, Chin-Ming Hong
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
14 years 1 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras