145 search results - page 29 / 29 » A Higher-Level Language for Hardware Synthesis |
FCCM
2007
IEEE
13 years 12 months ago
2007
IEEE
Programming efficiency of heterogeneous concurrent systems is limited by the use of lock-based synchronization mechanisms. Transactional memories can greatly improve the programmi...
CASES
2000
ACM
13 years 9 months ago
2000
ACM
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
EUROSYS
2007
ACM
13 years 7 months ago
2007
ACM
Hardware trends suggest that large-scale CMP architectures, with tens to hundreds of processing cores on a single piece of silicon, are iminent within the next decade. While exist...
CODES
2003
IEEE
13 years 10 months ago
2003
IEEE
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...