Sciweavers

19 search results - page 4 / 4
» A Large, Fast Instruction Window for Tolerating Cache Misses
Sort
View
HPCA
2005
IEEE
14 years 5 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...
HPCA
2008
IEEE
14 years 5 months ago
Address-branch correlation: A novel locality for long-latency hard-to-predict branches
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zho...
ISCA
2003
IEEE
110views Hardware» more  ISCA 2003»
13 years 10 months ago
Guided Region Prefetching: A Cooperative Hardware/Software Approach
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Ka...
BMCBI
2005
130views more  BMCBI 2005»
13 years 5 months ago
Squid - a simple bioinformatics grid
Background: BLAST is a widely used genetic research tool for analysis of similarity between nucleotide and protein sequences. This paper presents a software application entitled &...
Paulo C. Carvalho, Rafael V. Glória, Antoni...