18 search results - page 1 / 4 » A Logic-enhanced Memory for Digital Data Recovery Circuits |
ISCAS
1993
IEEE
13 years 9 months ago
1993
IEEE
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
EUROSYS
2008
ACM
14 years 2 months ago
2008
ACM
Programs written in type-unsafe languages such as C and C++ incur costly memory errors that result in corrupted data structures, program crashes, and incorrect results. We present...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
CCECE
2009
IEEE
13 years 9 months ago
2009
IEEE
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...