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ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
14 years 1 months ago
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
13 years 9 months ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan
HPCA
2011
IEEE
12 years 8 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
BMCBI
2010
218views more  BMCBI 2010»
13 years 5 months ago
Fast multi-core based multimodal registration of 2D cross-sections and 3D datasets
Background: Solving bioinformatics tasks often requires extensive computational power. Recent trends in processor architecture combine multiple cores into a single chip to improve...
Michael Scharfe, Rainer Pielot, Falk Schreiber
JSA
2010
158views more  JSA 2010»
12 years 11 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...