22 search results - page 3 / 5 » A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm |
ICIP
2001
IEEE
14 years 6 months ago
2001
IEEE
Shift variance and poor directional selectivity, two major disadvantages of the discrete wavelet transform, have previously been circumvented either by using highly redundant, non...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission ...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
: In this research, a fixed-point multimedia co-processor is designed and tested into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. Th...
TC
2010
13 years 3 months ago
2010
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
CAL
2007
13 years 5 months ago
2007
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...