28 search results - page 3 / 6 » A Mathematical Cache Miss Analysis for Pointer Data Structur... |
IEEEPACT
2006
IEEE
13 years 11 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
CODES
2001
IEEE
13 years 9 months ago
2001
IEEE
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
GLVLSI
2008
IEEE
14 years 6 days ago
2008
IEEE
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
CODES
2007
IEEE
14 years 2 days ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
PLDI
2005
ACM
13 years 11 months ago
2005
ACM
This paper describes Automatic Pool Allocation, a transformation framework that segregates distinct instances of heap-based data structures into seperate memory pools and allows h...