29 search results - page 2 / 6 » A Mechanism for Speculative Memory Accesses Following Synchr... |
CGO
2005
IEEE
13 years 11 months ago
2005
IEEE
Data speculative optimization refers to code transformations that allow load and store instructions to be moved across potentially dependent memory operations. Existing research w...
ICS
2003
Tsinghua U.
13 years 10 months ago
2003
Tsinghua U.
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
Only a handful of fundamental mechanisms for synchronizing the access of concurrent threads to shared memory are widely implemented and used. These include locks, condition variab...
ISCA
2006
IEEE
13 years 11 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
ISCA
1995
IEEE
13 years 8 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...