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DAC
2005
ACM
14 years 6 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
TC
2010
13 years 8 days ago
Model-Driven System Capacity Planning under Workload Burstiness
In this paper, we define and study a new class of capacity planning models called MAP queueing networks. MAP queueing networks provide the first analytical methodology to describe ...
Giuliano Casale, Ningfang Mi, Evgenia Smirni