1609 search results - page 322 / 322 » A Microeconomic Scheduler for Parallel Computers |
MOBICOM
2003
ACM
13 years 11 months ago
2003
ACM
We consider a two-tiered Wireless Sensor Network (WSN) consisting of sensor clusters deployed around strategic locations and base-stations (BSs) whose locations are relatively fl...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
CC
2006
Springer
13 years 9 months ago
2006
Springer
The polyhedral model is known to be a powerful framework to reason about high level loop transformations. Recent developments in optimizing compilers broke some generally accepted ...
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...