MICRO 2010 - PDF Preprint Papers

MICRO 2010 IEEE/ACM International Symposium on Microarchitecture

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MICRO
2010
IEEE

333views Hardware» more MICRO 2010»

Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor

13 years 3 months ago

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Pat Conway, Nathan Kalyanasundharam, Gregg Donley,...

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Id	Views	Title	Status

1	333	Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor	claim
2	270	Many-Thread Aware Prefetching Mechanisms for GPGPU Applications	claim
3	242	ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory	claim
4	238	Sampling Dead Block Prediction for Last-Level Caches	claim
5	215	A Task-Centric Memory Model for Scalable Accelerator Architectures	claim
6	210	Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior	claim
7	202	Hardware Support for Relaxed Concurrency Control in Transactional Memory	claim
8	189	A Dynamically Adaptable Hardware Transactional Memory	claim
9	186	Phase-Change Technology and the Future of Main Memory	claim
10	186	SAFER: Stuck-At-Fault Error Recovery for Memories	claim
11	175	Efficient Selection of Vector Instructions Using Dynamic Programming	claim
12	173	Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?	claim
13	172	Architectural Support for Fair Reader-Writer Locking	claim
14	170	Tolerating Concurrency Bugs Using Transactions as Lifeguards	claim
15	167	Erasing Core Boundaries for Robust and Configurable Performance	claim
16	161	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection	claim
17	159	Fractal Coherence: Scalably Verifiable Cache Coherence	claim
18	156	Explicit Communication and Synchronization in SARC	claim
19	154	Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory	claim
20	153	AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors	claim
21	153	Throughput-Effective On-Chip Networks for Manycore Accelerators	claim
22	153	Scalable Speculative Parallelization on Commodity Clusters	claim
23	149	ReMAP: A Reconfigurable Heterogeneous Multicore Architecture	claim
24	149	Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels	claim
25	146	The ZCache: Decoupling Ways and Associativity	claim
26	145	Combating Aging with the Colt Duty Cycle Equalizer	claim
27	144	3D Stacked Microprocessor: Are We There Yet?	claim
28	143	SD3: A Scalable Approach to Dynamic Data-Dependence Profiling	claim
29	142	Virtual Snooping: Filtering Snoops in Virtualized Multi-cores	claim
30	140	STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches	claim
31	140	Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories	claim
32	134	Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors	claim
33	132	Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches	claim
34	130	Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks	claim
35	128	Adaptive and Speculative Slack Simulations of CMPs on CMPs	claim
36	121	Rethinking Flash in the Data Center	claim
37	121	Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs	claim
38	121	Building Broadband Ahead of Digital Demand	claim
39	119	A Predictive Model for Dynamic Microarchitectural Adaptivity Control	claim
40	119	Task Superscalar: An Out-of-Order Task Pipeline	claim
41	115	Per-Thread Cycle Accounting	claim
42	111	Putting Faulty Cores to Work	claim
43	110	Technical Writing	claim
44	110	Digitization and Value Creation	claim
45	102	Gatekeeping Economics	claim
46	99	ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment	claim
47	98	InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing	claim
48	96	The Next Chapter at Google	claim
49	90	Moving Forward	claim

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