34 search results - page 2 / 7 » A Modular Memory BIST for Optimized Memory Repair |
CSREAESA
2009
13 years 6 months ago
2009
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
DAC
2011
ACM
12 years 5 months ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we give an overview of the trade-off to improve yield and optimize silicon manufacturing cost. The specific technology focus is on large embedded memories in comple...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-onchips (SOCs). To increase the utilization of memory redundancy, the BISR t...