36 search results - page 1 / 8 » A Near Optimal Algorithm for Technology Mapping Minimizing A... |
DAC
1992
ACM
13 years 9 months ago
1992
ACM
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
TCAD
1998
13 years 4 months ago
1998
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...