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DATE
2005
IEEE
126views Hardware» more  DATE 2005»
13 years 10 months ago
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits
We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI ...
Irith Pomeranz, Sudhakar M. Reddy
VTS
1997
IEEE
133views Hardware» more  VTS 1997»
13 years 9 months ago
ATPG for scan chain latches and flip-flops
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
Samy Makar, Edward J. McCluskey
ICCAD
2002
IEEE
85views Hardware» more  ICCAD 2002»
13 years 9 months ago
On undetectable faults in partial scan circuits
We study the undetectable faults in partial scan circuits under a test application scheme referred to as transparent-scan. The transparent-scan approach allows very aggressive tes...
Irith Pomeranz, Sudhakar M. Reddy
ICCD
2006
IEEE
105views Hardware» more  ICCD 2006»
13 years 11 months ago
A New Class of Sequential Circuits with Acyclic Test Generation Complexity
—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose t...
Chia Yee Ooi, Hideo Fujiwara
ICCAD
1994
IEEE
112views Hardware» more  ICCAD 1994»
13 years 9 months ago
Selecting partial scan flip-flops for circuit partitioning
This paper presents a new method of selecting scan ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
Toshinobu Ono