83 search results - page 2 / 17 » A New Combinational Logic Minimization Technique with Applic... |
DFT
2002
IEEE
13 years 9 months ago
2002
IEEE
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
ECAI
2004
Springer
13 years 10 months ago
2004
Springer
In this work we further investigate the relation, first found by Truszczy´nski, between modal logic S4F and Default Logic (DL), analyzing some interesting properties and showing ...
CADE
1998
Springer
13 years 9 months ago
1998
Springer
Abstract. The theorem prover Isabelle is used to formalise and reproduce some of the styles of reasoning used by Newton in his Principia. The Principia's reasoning is resolute...
DSN
2008
IEEE
13 years 6 months ago
2008
IEEE
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...