DFT 2002 - PDF Preprint Papers

DFT 2002 IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems

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DFT
2002
IEEE

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Matrix-Based Test Vector Decompression Using an Embedded Processor

13 years 9 months ago

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This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...

Kedarnath J. Balakrishnan, Nur A. Touba

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Id	Views	Title	Status

1	128	Matrix-Based Test Vector Decompression Using an Embedded Processor	claim
2	127	A New Functional Fault Model for FPGA Application-Oriented Testing	claim
3	121	Testing Digital Circuits with Constraints	claim
4	117	Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation	claim
5	115	Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis	claim
6	108	A Test-Vector Generation Methodology for Crosstalk Noise Faults	claim
7	103	Input Ordering in Concurrent Checkers to Reduce Power Consumption	claim
8	103	Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies	claim
9	102	Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems	claim
10	102	On-Chip Jitter Measurement for Phase Locked Loops	claim
11	79	Neural Networks-Based Parametric Testing of Analog IC	claim
12	79	Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm	claim

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