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ASPDAC
1998
ACM
72views Hardware» more  ASPDAC 1998»
13 years 9 months ago
A New Multiport Memory for High Performance Parallel Processor System with Shared Memory
K. Hirano, T. Ono, Hiroyuki Kurino, Mitsumasa Koya...
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
13 years 9 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
FPGA
2010
ACM
181views FPGA» more  FPGA 2010»
13 years 9 months ago
Efficient multi-ported memories for FPGAs
Multi-ported memories are challenging to implement with FPGAs since the provided block RAMs typically have only two ports. We present a thorough exploration of the design space of...
Charles Eric LaForest, J. Gregory Steffan
PDPTA
2003
13 years 7 months ago
Comparing Multiported Cache Schemes
The performance of the data memory hierarchy is extremely important in current and near future high performance superscalar microprocessors. To address the memory gap, computer de...
Smaïl Niar, Lieven Eeckhout, Koenraad De Boss...
IPPS
1998
IEEE
13 years 9 months ago
Performance Sensitivity of Space Sharing Processor Scheduling in Distributed-Memory Multicomputers
- Processor scheduling in distributed-memory systems has received considerable attention in recent years. Several commercial distributed-memory systems use spacesharing processor s...
Sivarama P. Dandamudi, Hai Yu